 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR 1/3-INCH 2-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Features * * * * * * * * * * * * DigitalClarityTM CMOS Imaging Technology High frame rate Superior low-light performance Low dark current Simple two-wire serial interface Auto black level calibration Support for long integration times 2 x 2 binning Anti-aliasing function Anti-eclipse function Operating modes: snapshot and flash control, high frame rate preview, electronic panning Programmable controls: gain, frame size/rate, exposure, left-right and top-bottom image reversal, window size, panning, zoom and decimation 10-bit analog-to-digital converter (ADC) with three external inputs Support for external mechanical shutter Internal master clock generated from on-chip phase locked loop (PLL) Electronic rolling shutter (ERS) PART NUMBERS: MT9D011W00STC MT9D011D00STC Table 1: Key Performance Parameters TYPICAL VALUE 1/3-inch (4:3) 4.48mm(H) x 3.36mm(V), 5.60mm Diagonal 1600H x 1200V 2.8m x 2.8m RGB Bayer Pattern Electronic Rolling Shutter (ERS) 40 MPS/40 MHz 15 fps at 36 MHz 30 fps at 36 MHz 10-bit, on-chip 1.0 V/lux-sec (550nm) 68dB 42dB 1.7V-3.6V 1.7V-1.9V (1.8V nominal) 2.5V-3.1V (2.8V nominal) 75mW at 30 fps, 36 MHz, Preview mode 125mW at 15 fps, (VAA, VAAPIX and VDD only) 36 MHz, Full frame mode -30C to +70C Wafer or die PARAMETER Optical Format Active Imager Size Active Pixels Pixel Size Color Filter Array Shutter Type Maximum Data Rate/ Master Clock Frame UXGA (full frame, Rate 1600H x 1200V) SVGA (preview, 800H x 600V) ADC Resolution Responsivity Dynamic Range SNRMAX Supply I/O Digital Voltage Core Digital Analog Power Consumption * * * * Applications * * * * Cellular phones PC cameras PDAs Toys and other battery-powered products Operating Temperature Packaging 09005aef81516da4 MT9D011__MI2010_E_1.fm - Rev. A 11/04 EN 1 (c)2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-Bit Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Double-Buffered Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Bad Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Changes to Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Changes to Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PLL Generated Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PLL Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Window Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Window Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Pixel Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Readout Speeds and Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Column Mirror Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Digital Zoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Binning Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Frame Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Minimum Horizontal Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Minimum Row Time Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Valid Data Signals Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 LINE_VALID Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 FRAME_VALID Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 09005aef81516da4 MT9D011_MI2010_ETOC.fm - Rev. A 11/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 2 PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Integration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Maximum Shutter Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Flash STROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Analog Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Stage-by-Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 VREFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gain Settings: G1, G2, G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Offset Voltage: VOFFSET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Recommended Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 PLL and Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Floating Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Dark Row/Column Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Analog Inputs AIN1-AIN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Hard Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Soft Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Propagation Delay for FRAME_VALID and LINE_VALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Propagation Delay for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 09005aef81516da4 MT9D011_MI2010_ETOC.fm - Rev. A 11/04 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Typical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Data Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 WRITE Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 READ Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 WRITE Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 READ Timing from Reg0x09; Returned Value 0x0284. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Eight Pixels in Normal and Column Skip 2x Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sixteen Pixels in Normal and Column Skip 4x Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Thirty-two Pixels in Normal and Column Skip 8x Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Sixty-four Pixels in Normal and Column Skip 16x Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Data from Pixel Array in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Data from Pixel Array in Zoom 2x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Data from Pixel Array in Zoom 4x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Data from Pixel Array in Zoom 8x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Data from Pixel Array in Zoom 16x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 LINE_VALID Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Early FRAME_VALID Rise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Early FRAME_VALID Fall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 LED Flash Enabled, Using Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Global Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Analog Readout Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Timing Diagram AIN1-AIN3 Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Propagation Delay for FRAME_VALID and LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Propagation Delays for PIXCLK and DOUT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface Write Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface Read Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Acknowledge Signal Timing Following 8-Bit Write to Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Acknowledge Signal Timing Following 8-Bit Read from Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Spectral Response (TBD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 09005aef81516da4 MT9D011_MI2010_ELOF.fm - Rev. A 11/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Frame--Long Integration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Register List and Default Value Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Skip Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Zoom Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Minimum Horizontal Blanking Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Minimum Row Time Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Offset Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Recommended Gain Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Output-Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Signal State During Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 09005aef81516da4 MT9D011_MI2010_ELOT.fm - Rev. A 11/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR General Description The Micron(R) Imaging MT9D011 is an oversize UXGA-format CMOS active-pixel digital image sensor with a pixel array of 1632H x 1216V. It incorporates sophisticated on-chip camera functions such as windowing, mirroring, row skip modes, and snapshot mode. It is programmable through a simple two-wire serial interface and achieves very low power consumption. The 2-megapixel CMOS image sensor features DigitalClarity--Micron's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. When operated in default mode, the sensor generates a UXGA image at 15 frames per second (fps). An on-chip ADC generates a 10-bit value for each pixel. The pixel data is output on a 10-bit output bus and qualified by an output data clock (PIXCLK), together with LINE_VALID and FRAME_VALID signals. A FLASH output strobe is provided to allow an external Xenon or LED light source to synchronize with the sensor exposure time. The sensor can be programmed by the user to control the frame size, exposure, gain setting, and other parameters. Figure 1: Block Diagram Control Register Active-Pixel Sensor (APS) Array UXGA 1600H x 1200V Timing and Control Serial I/O Sync Signals Analog Processing ADC Data Out Introduction The MT9D011 is a progressive-scan sensor that generates a stream of pixel data qualified by LINE_VALID and FRAME_VALID signals. An on-chip PLL generates the master clock from an input clock of 4 MHz to 40 MHz. In default mode, the data rate (pixel clock) is the same as the master clock frequency, which means that one pixel is generated every master clock cycle. The sensor block diagram is shown in Figure 1. The core of the sensor is an active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row. In the time interval between resetting a row and reading that row, the pixels in that row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. After a row is read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The pixel array contains optically active and light-shielded "black" pixels. The black pixels are used to provide data for on-chip offset correction algorithms ("black level" control). The sensor contains a set of 16-bit control and status registers that can be used to control many aspects of the sensor operations. These registers can be accessed through a two-wire serial interface. In this document, registers are specified either by name (e.g., column start) or by register address (e.g., Reg0x04). Fields within a register are specified by bit or by bit range (e.g., Reg0x20[0] or Reg0x0B[13:0]). The control and status registers are described in "Registers" on page 17. The output from the sensor is a Bayer pattern: alternate rows are a sequence of either green/red pixels or blue/green pixels. The offset and gain stages of the analog signal chain provide per-color control of the pixel data. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR The sensor generates a UXGA-sized image by default, with 10 parallel data outputs per pixel, and separate LINE_VALID, FRAME_VALID, and pixel clock outputs. All timing control is performed on-chip. Figure 2: Typical Configuration VDDQ VDD VAA VDDQ 1.5K1 1.5K1 VDD VAA VAAPIX VAAPLL DOUT [9:0] From Controller GRST_CTRL SADDR Clock (4 MHz-40 MHz) From Controller 1K CLKIN STANDBY SDATA SCLK MODE TEST RESET# DGND AGND PIXCLK LINE_VALID FRAME_VALID FLASH STROBE To Controller MT9D011 10F AIN12 AIN22 AIN32 DGND AGND NOTE: 1. Resistor value 1.5K is recommended, but may be greater for slower two-wire speed. 2. If not used, leave unconnected. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 2: NAME RESET# AIN1 AIN2 AIN3 SCLK SADDR STANDBY Signal Description TYPE Input Input Input Input Input Input Input DESCRIPTION Asynchronous active-low reset. When asserted, data output stops and all internal registers are restored to their factory default settings. Analog input port. If enabled by Reg0xE3, the pin is sampled once per row by the on-chip analog-to-digital converter (ADC). Similar to AIN1. Similar to AIN1. Serial clock for access to control and status registers. Selects the device address for the serial interface. See "Slave Address" on page 13. Multifunction pin to control device addressing, power-down, and pin tri-state functions. When LOW, the sensor functions normally. When HIGH, the sensor may enter a low-power state and may put certain outputs in a High-Z. "Power-Saving Modes" on page 53, "Output Enable Control" on page 51, and "Slave Address" on page 13. Input clock to PLL or master clock. Enable manufacturing test modes. Wire to DGND for functional operation. Tie to DGND for normal operation. Serial data for reads from and writes to control and status registers. Pixel data output 9 (most significant bit (MSB)). Pixel data output 8. Pixel data output 7. Pixel data output 6. Pixel data output 5. Pixel data output 4. Pixel data output 3. Pixel data output 2. Pixel data output 1. Pixel data output 0 (least significant bit (LSB)). LINE_VALID. Asserted during a line of valid pixel data. (The operation of this signal can be controlled by Reg0x25[15:14].) FRAME_VALID. Asserted during a frame of valid pixel data. Pixel clock. By default, pixel data, LINE_VALID, and FRAME_VALID are valid on the rising edge of this clock. This signal can be inverted and delayed under the control of Reg0x0A. Synchronization pulse for mechanical shutter in global reset mode. Controls the global reset operation. Synchronization pulse for external light source. I/O power. Digital power. Digital and I/O ground. PLL power. Analog power. Analog ground. Analog power for pixel array. CLKIN TEST MODE SDATA DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 LINE_VALID FRAME_VALID PIXCLK STROBE GRST_CTR FLASH VDDQ VDD DGND VAAPLL VAA AGND VAAPIX Input Input Input I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Power Power Power Power Power Power Power 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Pixel Array Structure The MT9D011 pixel array is configured as 1688 columns by 1256 rows (shown in Figure 3). The first 52 columns and the first and the last 20 rows of pixels are optically black and are used for the automatic black level adjustment. The last four columns are also optically black. The optically active pixels are used as follows: In default mode a UXGA image (1600 columns by 1200 rows) is generated, starting at row 28, column 60. A four-pixel boundary of active pixels can be enabled around the image to avoid boundary effects during color interpolation and correction. During mirrored readout, the region of active pixels used to generate the image is offset by one pixel in each mirrored direction so that the readout always starts on the same color pixel. Figure 4: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction . . . Black Pixels First Clear Pixel (52,20) G1 R G1 R G1 R G1 Row Readout Direction B G2 B G2 B G2 B ... G1 R G1 R G1 R G1 B G2 B G2 B G2 B G1 R G1 R G1 R G1 B G2 B G2 B G2 B Figure 3: Pixel Array (0,0) 20 black rows Default Readout Order Oversize UXGA 4 black columns 1632 x 1216 active pixels 52 black columns 20 black rows (1687,1255) By convention, the MT9D011 pixel array is shown with pixel (0,0) in the top right-hand corner (see Figure 4). This reflects the actual layout of the array on the die. When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 5. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 3. By convention, data from the sensor is shown with the first pixel read out--pixel (52,20) in the case of the MT9D011--in the top left-hand corner. See Figure 6. Figure 5: Imaging a Scene The MT9D011 uses a Bayer color pattern as shown in Figure 4. The even-numbered rows contain green and red color pixels; odd-numbered rows contain blue and green color pixels. Even-numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. The color order is preserved during mirrored readout. Lens Scene Sensor (rear view) Row Readout Order Column Readout Order Pixel(0,0) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Output Data Format MT9D011 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking as shown in Figure 6. The amount of horizontal and vertical blanking is programmable. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in the next section. Output Data Timing MT9D011 output data is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one pixel datum is output on the 10-bit DOUT output every PIXCLK period. By default, the PIXCLK signal runs at the same frequency as the master clock, and its rising edges occur one-half of a master clock period after transitions on LINE_VALID, FRAME_VALID, and DOUT (see Figure 7). This allows PIXCLK to be used as a clock to sample the data. PIXCLK is continuously enabled, even during the blanking period. The MT9D011 can be programmed to delay the PIXCLK edge relative to the DOUT transitions from 0 to 3.5 master clocks, in steps of one-half of a master clock. This can be achieved by programming the corresponding bits in Reg0x0A. The parameters P A, and Q in Figure 8 are defined in , Table 3 on page 12. Figure 6: Spatial Illustration of Image Readout P0,0 P0,1 P0,2................................P0,n-1 P0,n P1,0 P1,1 P1,2................................P1,n-1 P1,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1.........................Pm-1,n-1 Pm-1,n Pm,0 Pm,1.........................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ................................ 00 00 00 00 00 00 ................................ 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 Figure 7: Pixel Data Timing Example LINE_VALID PIXCLK Blanking Valid Image Data Blanking DOUT[9:0] P0 (9:0) P1 (9:0) P2 (9:0) P3 (9:0) P4 (9:0) Pn-1 (9:0) Pn (9:0) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals FRAME_VALID LINE_VALID Number of master clocks P A Q A Q A P The sensor timing (Table 3) is shown in terms of pixel-clock and master-clock cycles (see Figure 7 on page 10). The recommended master clock frequency is 36 MHz. Increasing the integration time to more than one frame will cause the frame time to be extended. The equations in Table 3 assume integration time is less than the number of rows in a frame (Reg0x09 < Reg0x03/S + BORDER + VBLANK_REG). If this is not the case, the number of integration rows must be used instead to determine the frame time as shown in Table 4. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 3: PARAMETER HBLANK_REG VBLANK_REG ADC_MODE PIXCLK_PERIOD S Frame Time NAME Horizontal Blanking Register Vertical Blanking Register ADC mode Pixel clock period Skip Factor EQUATION Reg0x07 if Reg0xF2[0] = 0 Reg0x05 if Reg0xF2[0] = 1 Reg0x8 if Reg0xF2[1] = 0 Reg0x6 if Reg0xF2[1] = 1 Reg0xF2[3] = 0: Reg0x20[10] Reg0xF2[3] = 1: Reg0x21[10] ADC_MODE = 0: Reg0x0A[2:0] ADC_MODE = 1: Reg0x0A[2:0]*2 For skip 2x mode: S = 2 For skip 4x mode: S = 4 For skip 8x mode: S = 8 For skip 16x mode: S = 16 otherwise, S = 1 (Reg0x04/S) * PIXCLK_PERIOD DEFAULT TIMING AT 36 MHZ, DUAL ADC MODE 0x15C = 348 pixels 0x20 = 32 rows 1 ADC_MODE: 55.556ns 2 ADC_MODE: 27.778ns 1 A Active Data Time P Frame Start/End Blanking 6 * PIXCLK_PERIOD (can be controlled by Reg0x1F) Q Horizontal Blanking HBLANK_REG * PIXCLK_PERIOD A+Q RowTime ((Reg0x04/S) + HBLANK_REG) * PIXCLK_PERIOD V Vertical Blanking VBLANK_REG * (A + Q) + (Q - 2*P) Nrows * (A+Q) Frame Valid Time (Reg0x03/S) * (A + Q) - (Q - 2*P) F Total Frame Time ((Reg0x03/S) + VBLANK_REG) * (A + Q) 1,600 pixel clocks = 1,600 master = 44.44s 6 pixel clocks = 12 master = 0.166s 348 pixel clocks = 348 master = 9.667s 1,948 pixel clocks = 1,948 master = 54.112s 62,672 pixel clocks = 62,672 master = 1.741ms 2,337,264 pixel clocks = 2,337,264 master = 64.925ms 2,399,936 pixel clocks = 2,399,936 master = 66.665ms NOTE: 1. Skip factor should be multiplied by 2 if binning is enabled. Table 4: PARAMETER V' F' Frame--Long Integration Time NAME Vertical Blanking (long integration time) Total Frame Time (long integration time) EQUATION (MASTER CLOCK) (Reg0x09-(Reg0x03)/S)*(A + Q) + (Q - 2*P) (Reg0x09)*(A + Q) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Two-Wire Serial Register Interface This section describes the two-wire serial interface bus that can be used in any functional sensor mode. The two-wire serial interface bus enables R/W access to control and status registers within the MT9D011. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and used to synchronize transfers. The master is responsible for driving a valid logic level on SCLK at all times. Data is transferred between the master and the slave on a bidirectional signal (SDATA). The SDATA signal is pulled up to VDD off-chip by a 1.5k resistor. Either the slave or master device can drive the SDATA line low--the interface protocol determines which device is allowed to drive the SDATA line at any given time. The MT9D011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. 1. The master sends the write-mode slave address and 8-bit register address, just as in the write request. 2. The master then sends a start bit and the readmode slave address, and clocks out the register data, eight bits at a time. 3. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. 4. The data transfer is stopped when the master sends a no-acknowledge bit. Protocol The two-wire serial interface bus defines the transmission codes as follows: * a start bit * the slave device 8-bit address * a(an) (no) acknowledge bit * an 8-bit message * a stop bit Bus Idle State The bus is idle when both the data and clock lines are high. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW data line transition while the clock line is HIGH. Sequence A typical read or write sequence is executed as follows: 1. The master sends a start bit. 2. The master sends the 8-bit slave device address. The last bit of the address determines if the request is a read or a write, where a "0" indicates a write and a "1" indicates a read. 3. The slave device acknowledges receipt of the address by sending an acknowledge bit to the master. 4. If the request is a write, the master then transfers the 8-bit register address, indicating where the write takes place. 5. The slave sends an acknowledge bit, indicating that the register address has been received. 6. The master then transfers the data, eight bits at a time, with the slave sending an acknowledge bit after each eight bits. Stop Bit The stop bit is defined as a lLOW-to-HIGH data line transition while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and one bit of direction. A "0" in the LSB (least significant bit) of the address indicates write mode, and a "1" indicates read mode. The default slave addresses used by the MT9D011 are 0xBA (write address) and 0xBB (read address). Reg0x0D[10] or the SADDR pin can be used to select the alternate slave addresses 0x90 (write address) and 0x91 (read address). Writes to Reg0x0D[10] are inhibited when the standby pin is asserted (all other writes proceed normally). This allows two sensors to co-exist as slaves on this interface, but they must be addressed independently. Enable this capability as follows: 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR After RESET, both sensors use the default slave address. Reads or writes on the serial register interface to the default slave address are decoded by both sensors simultaneously. 1. After RESET, assert the STANDBY signal to one sensor and negate the STANDBY signal to the other sensor. 2. Perform a write to Reg0x0D with bit 10 set. The sensor with STANDBY asserted ignores the write to bit 10 and continues to decode at the default slave address. The sensor with STANDBY negated has its Reg0x0D[10] set and responds to the alternate slave address for all subsequent read and write operations, as shown in See Table 5. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. Page Register The MT9D011 two-wire serial interface and its associated protocols support an address space of 256 16-bit locations. This address space can be extended by a 3bit page prefix, and controlled through accesses to Reg0xF0. The paging mechanism is intended to allow access to other sets of registers when the sensor is embedded as part of a more complex integrated subsystem, for example, in an SOC. All registers within the MT9D011 are accessible on page 0 (the default page). Table 5: SADDR PIN 0 0 1 1 Slave Address Options SLAVE ADDRESS REG0XD[10] 0 1 0 1 WRITE 0x090 0x0BA 0x0BA 0x090 READ 0x091 0x0BB 0x0BB 0x091 Sample Write and Read Sequences 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master starts the sequence, followed by the write address. The image sensor then sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the high period of the two-wire serial interface clock--it can only change when the serial clock is low. Data is transferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. Figure 9: WRITE Timing to R0x09:0--Value 0x0284 SCLK SDATA 0xBA Address Start ACK Reg0x09 ACK 0000 0010 ACK 1000 0100 Stop ACK 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR 16-Bit Read Sequence A typical read sequence is shown in Figure 10. First the master writes the register address, as in a write sequence. Then a start bit and the read address specify that a read is about to happen from the register. The master clocks out the register data, eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Figure 10: READ Timing from R0x09:0; Returned Value 0x0284 SCLK SDATA 0xBA Address Start ACK ACK Reg0x09 0xBB Address Start ACK ACK NACK 0000 0010 1000 0100 Stop 8-Bit Write Sequence To be able to write one byte at a time to the register, a special register address is added. The 8-bit write is done by writing the upper 8 bits to the desired register, then writing the lower 8 bits to the special register address (Reg0xF1). The register is not updated until all 16 bits have been written. It is not possible to update just half of a register. In Figure 11, a typical sequence for 8-bit writes is shown. The second byte is written to the special register (Reg0xF1). Figure 11: WRITE Timing to R0x09:0--Value 0x0284 SCLK SDATA 0xBA Address Start ACK Reg0x09 ACK 0000 0010 ACK 0xBA Address Start ACK Reg0xF1 ACK 1000 0100 Stop ACK 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR 8-Bit Read Sequence To read one byte at a time, the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a read from the special register (Reg0xF1), the lower 8 bits are accessed (Figure 12). The master sets the noacknowledge bits shown. Figure 12: READ Timing from Reg0x09; Returned Value 0x0284 SCLK SDATA 0xBA Address Start ACK ACK Reg0x09 0xBB Address Start ACK NACK 0000 0010 ** SCLK SDATA ** 0xBA Address Start ACK Reg0xF1 ACK 0xBB Address Start ACK 1000 0100 Stop NACK 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Registers The MT9D011 provides a register address space of 256 locations. or written to. Locations that are shown in the table as Reserved are not to be read from or written to. The effect of doing so is UNDEFINED and may include the possibility of causing permanent electrical damage to the sensor. Register Map Table 6 shows the locations used within the address space. Locations that are not shown in the table are reserved for future use; they should not be read from Table 6: Register List and Default Value Descriptions DESCRIPTION Chip Version Row Start Column Start Row Width Column Width Horizontal Blanking--Context B Vertical Blanking--Context B Horizontal Blanking--Context A Vertical Blanking--Context A Shutter Width Row Speed Extra Delay Shutter Delay Reset FRAME_VALID Control Read Mode--Context B Read Mode--Context A Dark Columns/Rows Flash Extra Reset LINE_VALID Control Bottom Dark Rows Green1 Gain Blue Gain Red Gain Green2 Gain Global Gain Row Noise Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT (BINARY) 0001 0101 0001 0001 (LSB) 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd dddd dddd dddd dddd ddd0 0000 dddd 0ddd 00dd dddd dddd dddd 00dd dddd dddd dddd d000 0ddd dddd 0ddd dddd dddd dddd dddd d0dd dddd dddd dddd d000 0d00 dddd dd00 0000 0ddd dddd dddd ??dd dddd dddd dddd dd00 0000 0000 0000 dd00 0000 0000 0000 0000 0000 dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- DEFAULT VALUE (HEX) 0x1511 0x001C 0x003C 0x04B0 0x0640 0x015C 0x0020 0x00AE 0x0010 0x04D0 0x0011 0x0000 0x0000 0x0000 0x0000 0x0000 0x0490 0x010F 0x0608 0x8000 0x0000 0x0007 0x0020 0x0020 0x0020 0x0020 0x0020 0x042A 0x0000 0x02AA 0x0341 0x000F 0x0EE8 0xF0F0 0x0808 0x0020 0x2020 REGISTER #DEC (HEX) 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 31 (0x1F) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24) 37 (0x25) 38 (0x26) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 51 (0x33) 52 (0x34) 53 (0x35) 54 (0x36) 56 (0x38) 59 (0x3B) 60 (0x3C) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 6: Register List and Default Value Descriptions (continued) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Black Rows Reserved Dark G1 Average Dark B Average Dark R Average Dark G2 Average Calib Threshold Calib Control Calib Green1 Calib Blue Calib Red Calib Green2 Clock Control PLL Control 1 PLL Control 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT (BINARY) -- -- -- -- -- -- -- -- -- 0000 0000 dddd dddd -- 0000 0000 0??? ???? 0000 0000 0??? ???? 0000 0000 0??? ???? 0000 0000 0??? ???? 0ddd dddd 0ddd dddd d00d 0ddd dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd 0000 000d dddd dddd ddd0 0000 0000 dddd dddd dddd 00dd dddd 0000 dddd 0ddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE (HEX) 0x2000 0x0020 0x1000 0x0000 0x00D7 0x0077 0x87FF 0x0002 0x0000 0x00FF 0xE2DF N/A N/A N/A N/A 0x231D 0x0080 0x0000 0x0000 0x0000 0x0000 0xe000 0x2809 0x0501 0xAD01 0x893F 0xB502 0xB502 0x2B03 0x1A12 0x8850 0x705F 0xAC57 0x4F28 0xB301 0xB309 0xB00F 0xFF00 0xB601 0xAE56 0x00B7 0xAD1A 0x8402 0x8404 0x8103 REGISTER #DEC (HEX) 61 (0x3D) 62 (0x3E) 63 (0x3F) 63 (0x40) 65 (0x41) 66 (0x42) 86 (0x56) 87 (0x57) 88 (0x58) 89 (0x59) 90 (0x5A) 91 (0x5B) 92 (0x5C) 93 (0x5D) 94 (0x5E) 95 (0x5F) 96 (0x60) 97 (0x61) 98 (0x62) 99 (0x63) 100 (0x64) 101 (0x65) 102 (0x66) 103 (0x67) 110 (0x6E) 111 (0x6F) 112 (0x70) 113 (0x71) 114 (0x72) 115 (0x73) 116 (0x74) 117 (0x75) 118 (0x76) 119 (0x77) 120 (0x78) 121 (0x79) 122 (0x7A) 123 (0x7B) 124 (0x7C) 125 (0x7D) 126 (0x7E) 127 (0x7F) 128 (0x80) 129 (0x81) 130 (0x82) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 6: Register List and Default Value Descriptions (continued) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Global Shutter Control Start Integration (T1) Start Readout (T2) Assert Strobe (T3) De-assert Strobe (T4) Assert Flash De-assert Flash Reserved Reserved Reserved DATA FORMAT (BINARY) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- d000 0000 0000 0ddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd -- -- -- DEFAULT VALUE (HEX) 0x261C 0x6D06 0x3423 0x8701 0x0088 0x6E03 0x8201 0x7B6F 0xFFFF 0x715E 0x8A79 0x897A 0x2319 0xFFFF 0x1B11 0xAE21 0xAD22 0x4733 0xFFFF 0x3522 0x6F45 0x6E46 0x3525 0xFFFF 0x271B 0x8333 0x8234 0x1A00 0x1901 0x1802 0x1A00 0x1901 0x1802 0x002C 0x001A 0x0000 0x0064 0x0064 0x0096 0x00C8 0x0064 0x0078 0x4E20 0x0258 0x1F40 REGISTER #DEC (HEX) 131 (0x83) 132 (0x84) 133 (0x85) 134 (0x86) 135 (0x87) 136 (0x88) 137 (0x89) 144 (0x90) 145 (0x91) 146 (0x92) 147 (0x93) 148 (0x94) 149 (0x95) 150 (0x96) 151 (0x97) 152 (0x98) 153 (0x99) 160 (0xA0) 161 (0xA1) 162 (0xA2) 163 (0xA3) 164 (0xA4) 165 (0xA5) 166 (0xA6) 167 (0xA7) 168 (0xA8) 169 (0xA9) 176 (0xB0) 177 (0xB1) 178 (0xB2) 179 (0xB3) 180 (0xB4) 181 (0xB5) 182 (0xB6) 183 (0xB7) 192 (0xC0) 193 (0xC1) 194 (0xC2) 195 (0xC3) 196 (0xC4) 197 (0xC5) 198 (0xC6) 199 (0xC7) 200 (0xC8) 201 (0xC9) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 6: Register List and Default Value Descriptions (continued) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved External Sample 1 External Sample 2 External Sample 3 External Sampling Control Page Register Bytewise Address Context Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chip Version DATA FORMAT (BINARY) -- -- -- -- -- -- 0000 00?? ???? ???? 0000 00?? ???? ???? 0000 00?? ???? ???? dd00 0000 0000 0000 0000 0000 0000 0ddd 0000 0000 0000 0000 d000 0000 d000 dddd -- -- -- -- -- -- -- -- -- 0001 0101 0001 0001 DEFAULT VALUE (HEX) 0x001E 0x001C 0x003C 0x04BC 0x0654 0x00B0 N/A N/A N/A 0x0000 0x0000 0x0000 0x000B 0x07FF 0x07FF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x1511 REGISTER #DEC (HEX) 202 (0xCA) 208 (0xD0) 209 (0xD1) 210 (0xD2) 211 (0xD3) 212 (0xD4) 224 (0xE0) 225 (0xE1) 226 (0xE2) 227 (0xE3) 240 (0xF0) 241 (0xF1) 242 (0xF2) 245 (0xF5) 246 (0xF6) 247 (0xF7) 248 (0xF8) 249 (0xF9) 250 (0xFA) 251 (0xFB) 252 (0xFC) 253 (0xFD) 255 (0xFF) NOTE: 1 = always 1 0 = always 0 d = programmable ? = read-only (R/O) R/W = Read/Write 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Register Description Table 7 provides a detailed description of the registers. Bit fields that are not identified in the table are read only. Double-Buffered Registers Some sensor settings cannot be changed during frame readout. For example, changing row width Reg0x03 part way through frame readout results in inconsistent LINE_VALID behavior. To avoid this, the MT9D011 double buffers many registers by implementing a "pending" and a "live" version. Reads and writes access the pending register. The live register controls the sensor operation. The value in the pending register is transferred to a live register at a fixed point in the frame timing, called "frame start." Frame start is defined as the point at which the first dark row is read out. By default, this occurs ten row times before FRAME_VALID goes high. Reg0x22 enables the dark rows to be shown in the image, but this has no effect on the position of frame start. To determine which registers or register fields are double-buffered in this way, see Table 7, the "sync'dto-frame-start" column. Reg0x0D[15] can be used to inhibit transfers from the pending to the live registers. This control bit should be used when making many register changes that must take effect simultaneously. Bad Frames A bad frame is a frame where all rows do not have the same integration time, or where offsets to the pixel values changed during the frame. Many changes to the sensor register settings can cause a bad frame. For example, when row width Reg0x03 is changed, the new register value does not affect sensor behavior until the next frame start. However, the frame that would be read out at that framestart has been integrated using the old row width. Consequently, reading it out using the new row width results in a frame with an incorrect integration time. By default, most bad frames are masked: LINE_VALID and FRAME_VALID are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. To determine which register or register field changes can produce a bad frame, see Table 7, the "bad frame" column, and these notations: * N--No. Changing the register value does not produce a bad frame. * Y--Yes. Changing the register value might produce a bad frame. * YM--Yes; but the bad frame is masked out unless the "show bad frames" feature (Reg0x0D[8]) is enabled. Changes to Integration Time If the integration time (Reg0x09) is changed while FRAME_VALID is asserted for frame n, the first frame output using the new integration time is frame (n+2). The sequence is as follows: 1. During frame n, the new integration time is held in the Reg0x09 pending register. 2. At the start of frame (n+1), the new integration time is transferred to the Reg0x09 live register. Integration for each row of frame (n+1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n+1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n+1) is read out, it is integrated using the new integration time. If the integration time is changed (Reg0x09 written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. Changes to Gain Settings When the gain settings (Reg0x2B, Reg0x2C, Reg0x2D, Reg0x2E, and Reg0x2F) are changed, the gain is usually updated on the next frame start. When the integration time and the gain are changed simultaneously, the gain update is held off by one frame so that the first frame output with the new integration time also has the new gain applied. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR r Table 7: BIT FIELD R0--0X00 - CHIP VERSION (R/O) Bits 15:0 Bits 10:0 Chip Version Row Start Chip version. The first row to be read out, excluding any dark rows that may be read. To window the image down, set this register to the starting "Y" value. Setting a value less than 20 is not recommended because the dark rows should be read using Reg0x22. The first column to be read out, excluding dark columns that may be read. To window the image down, set this register to the starting X value. Setting a value below 52 is not recommended because readout of dark columns should be controlled by Reg0x22. Number of rows in the image to be read out, excluding any dark rows or border rows that may be read. The minimum supported value is 2. 1511 1C Y YM R1--0X01 - ROW START (R/W) Register Description DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R2--0X02 - COLUMN START (R/W) Bits 10:0 Column Start 3C Y YM R3--0X03 - ROW WIDTH (R/W) Bits 10:0 Row Width 4B0 Y YM R4--0X04 - COLUMN WIDTH (R/W) Bits 10:0 Column Width Number of columns in image to be read out, excluding any dark columns or border columns that may be read. The minimum supported value is 9 in 1 ADC mode and 17 in 2 ADC mode. Horizontal Blanking-- Context B Number of blank columns in a row when Context B is selected (Reg0xF2[0] = 1). The extra columns are added at the beginning of a row. "Frame Rate Control" on page 43 for more information on supported register values. Number of blank rows in a frame when Context B is selected (Reg0xF2[1] = 1). The minimum supported value is (4 + Reg0x22[2:0]). The actual vertical blanking time may be controlled by the shutter width (Reg0x9); see "Output Data Timing" on page 10. Number of blank columns in a row when Context A is selected (Reg0xF2[0] = 0). The extra columns are added at the beginning of a row. "Frame Rate Control" on page 43 for more information on supported register values. 640 Y YM R5--0X05 - HORIZONTAL BLANKING--CONTEXT B (R/W) Bits 13:0 15C Y YM R6--0X06 - VERTICAL BLANKING--CONTEXT B (R/W) Bits 14:0 Vertical Blanking-- Context B 20 Y N R7--0X07 - HORIZONTAL BLANKING--CONTEXT A (R/W) Bits 13:0 Horizontal Blanking-- Context A AE Y YM 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R8--0X08 - VERTICAL BLANKING--CONTEXT A (R/W) Bits 14:0 Vertical Blanking-- Context A Number of blank rows in a frame when Context A is chosen (Reg0xF2[1] = 1). The minimum supported value is (4 + Reg0x22[2:0]). The actual vertical blanking time may be controlled by the shutter width (Reg0x9); see "Output Data Timing" on page 10. 10 Y N R9--0X09 - SHUTTER WIDTH (R/W) Bits 15:0 Shutter Width Integration time in number of rows. The integration time is also influenced by the shutter delay (Reg0x0C) and the overhead time. Do not change from default value. Do not change from default value. Invert PIXCLK. When clear, FRAME_VALID, LINE_VALID, and DOUT are set up relative to the delayed rising edge of PIXCLK. When set, FRAME_VALID, LINE_VALID, and DOUT are set up relative to the delayed falling edge of PIXCLK. Number of half master clock cycle increments to delay the rising edge of PIXCLK relative to transitions on FRAME_VALID, LINE_VALID, and DOUT. Do not change from default value. . A programmed value of N gives a pixel clock period of N master clocks in 2 ADC mode and 2*N master clocks in 1 ADC mode. A value of "0" is treated like (and reads back as) a value of "1." Extra blanking inserted between frames. A programmed value of N increases the vertical blanking time by N pixel clock periods. Can be used to get a more exact frame rate. It may affect the integration times of parts of the image when the integration time is less than one frame. The amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. If the value in this register exceeds the row time, the reset of the row does not complete before the associated row is sampled, and the sensor does not generate an image. A programmed value of N reduces the integration time by (N/2) pixel clock periods in 1 ADC mode and by N pixel clock periods in 2 ADC mode. 4D0 Y N R10--0X0A - ROW SPEED (R/W) Bits 15:14 Reserved Bit 13 Reserved Bit 8 Invert Pixel Clock 0 N N Bits 7:4 Delay Pixel Clock Reserved Pixel Clock Speed 1 N N Bit 3 Bits 2:0 1 Y YM R11--0X0B - EXTRA DELAY (R/W) Bits 13:0 Extra Delay 0 Y N2 R12--0X0C - SHUTTER DELAY (R/W) Bits 13:0 Shutter Delay 0 Y N 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD R13--0X0D - RESET (R/W) Bit 15 By default, update of many registers are synchronized to frame start. Setting this bit inhibits this update; register changes remain pending until this bit is returned to "0." When this bit is returned to "0," all pending register updates are made on the next frame start. Toggle SADDR By default, the sensor serial bus responds to addresses 0xBA and 0xBB. When this bit is set, the sensor serial bus responds to addresses 0x90 and 0x91. Writes to this bit are ignored when STANDBY is asserted. "Slave Address" on page 13. Restart Bad When set, a restart is forced to take place whenever a bad Frames frame is detected. This can shorten the delay when waiting for a good frame because the delay, when masking out a bad frame, is the integration time rather than the full frame time. Show Bad 1: Output all frames (including bad frames). Frames 0: Only output good frames (default). A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, binning, mirroring, or use of border. Inhibit Standby By default, asserting STANDBY places the sensor in a lowpower state. Setting this bit stops STANDBY from affecting entry to or exit from the low-power state. See "PowerSaving Modes" on page 53. Drive Pins By default, asserting STANDBY causes the pin interface to enter a High-Z. Setting this bit stops STANDBY from contributing to output-enable control. See "Output Enable Control" on page 51. Reserved Do not change from default value. Output Disable Setting this bit puts the pin interface in a High-Z. See "Output Enable Control" on page 51. Reserved Do not change from default value. Standby Setting this bit places the sensor in a low-power state. See "Power-Saving Modes" on page 53. Restart Setting this bit causes the sensor to truncate the current frame and start resetting the first row. The delay before the first valid frame is read out is equal to the integration time. This bit is write -1 but always reads back as 0. Synchronize Changes 0 N N Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME Bit 10 0 N N Bit 9 0 N N Bit 8 0 N N Bit 7 0 N N Bit 6 0 N N Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 N N YM YM 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bit 0 Reset Register Description (continued) DESCRIPTION Setting this bit puts the sensor in reset; the frame being generated is truncated and the pin interface goes to an idle state. All internal registers (except for this bit) go to the default power-up state. Clearing this bit resumes normal operation. DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 0 N YM R31--0X1F - FRAME_VALID CONTROL (R/W) Bit 15 Enable Early 1: Enables the early disabling of FRAME_VALID as set in bits FRAME_VALID 14:8. Note that LINE_VALID is still generated for all active Fall rows. 0: Default. FRAME_VALID goes low 6 pixel clocks after last LINE_VALID. Early When enabled, the FRAME_VALID falling edge occurs within FRAME_VALID the programmed number of rows before the end of the last Fall LINE_VALID. (1 + bits 14:8)*row time + constant (constant = 3 in default mode) The value of this field must not be larger than row width Reg0x03. Enable Early 1: Enables the early rise of FRAME_VALID as set in bits 6:0. FRAME_VALID 0: Default. FRAME_VALID goes high 6 pixel clocks before Rise first LINE_VALID. Early When enabled, the FRAME_VALID rising edge is set HIGH FRAME_VALID the programmed number of rows before the first Rise LINE_VALID: (1 + bits 6:0)*row time + horizontal blank + constant (constant = 3 in default mode). Binning-- Context B When Read mode Context B is selected (Reg0xF2[3] = 1): 0: Normal operation. 1: Binning enabled. See "Binning" on page 42 and "Frame Rate Control" on page 43 for a full description. 0: Normal operation. 1: Zoom is enabled, with zoom factor [zoom] defined in bits 12:11. In zoom mode, the pixel data rate is slowed by a factor of [zoom]. This is achieved by outputting [zoom-1] blank rows between each output row. Setting this mode allows the user to fill a window that is [zoom] times larger with interpolated data. The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for [zoom] pixel clocks. Every row is followed by [zoom-1] blank rows (with their own LINE_VALID, but all data bits = 0) of equal time. The combination of this register and an appropriate change to the window sizing registers allows the user to zoom to a region of interest without affecting the frame rate. 0 N N Bits 14:8 0 N N Bit 7 0 N N Bits 6:0 0 N N R32--0X20 - READ MODE--CONTEXT B (R/W) Bit 15 0 Y YM Bit 13 Zoom Enable 0 Y YM 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bits 12:11 Zoom Register Description (continued) DESCRIPTION When zoom is enabled by bit 13, this field determines the zoom amount: "00"--Zoom 2x. "01"--Zoom 4x. "10"--Zoom 8x. "11"--Zoom 16x. DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 0 Y YM Bit 10 Use 1 ADC-- Context B Bit 9 Bit 8 Bit 7 Bits 6:5 Bit 4 Bits 3:2 When Read mode Context B is selected (bit 3, Reg0xF2 = 1): 0: Use both ADCs to achieve maximum speed. 1: Use 1 ADC to reduce power. Maximum readout frequency is now half the master clock frequency, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Show Border This bit indicates whether to show the border enabled by bit 8. "X0"--Normal behavior, no border. "01"--Border is enabled but not shown; vertical blanking is increased by eight rows and horizontal blanking is increased by eight pixels. "11"--border is enabled and shown; FRAME_VALID time is extended by 8 rows and LINE_VALID is extended by 8 pixels. See "Pixel Border" on page 36. Over Sized When this bit is set, a four-pixel border is output around the active image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit adds eight to the number of rows and columns in the frame. Column Skip When Read mode Context B is selected (Reg0xF2[3] = 1): Enable-- 1: Enable column skip. Context B 0: Normal readout. Column Skip-- When Read mode Context B is selected (Reg0xF2[3] = 1) and Context B column skip is enabled (bit 7 = 1): "00"--Column Skip 2x. "01"--Column Skip 4x. "10"--Column Skip 8x. "11"--Column Skip 16x. See "Column and Row Skip" on page 38 for more information. Row Skip When Read mode Context B is selected (Reg0xF2[3] = 1): Enable-- 1: Enable row skip. Context B 0: Normal readout. Row Skip-- When Read mode Context B is selected (Reg0xF2[3] = 1) and Context B Row skip is enabled (bit 4 = 1): "00"--Row Skip 2x. "01"--Row Skip 4x. "10"--Row Skip 8x. "11"--Row Skip 16x. See "Column and Row Skip" on page 38 for more information. 0 Y YM 0 N N 0 Y YM 0 Y YM 0 Y YM 0 Y YM 0 Y YM 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bit 1 Register Description (continued) DESCRIPTION Mirror Columns Read out columns from right to left (mirrored). When set, column readout starts from column (Column Start + Column Size) and continues down to (Column Start + 1). When clear, readout starts at Column Start and continues to (Column Start + Column Size - 1). This ensures that the starting color is maintained. Mirror Rows Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Row Size) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size 1). This ensures that the starting color is maintained. When Read mode Context A is selected (Reg0xF2[3] = 0): 0: Normal operation. 1: Binning enabled. "Binning" on page 42. Use 1 ADC-- When Read mode Context A is selected (Reg0xF2[3] = 0): Context A 0: Use both ADCs to achieve maximum speed. 1: Use one ADC to reduce power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Column Skip When Read mode Context A is selected (Reg0xF2[3] = 0): Enable-- 1: Enable column skip. Context A 0: Normal readout. Column Skip-- When Read mode Context A is selected (Reg0xF2[3] = 0) and Context A column skip is enabled (bit 7 = 1): "00"--Column Skip 2x. "01"--Column Skip 4x. "10"--Column Skip 8x. "11"--Column Skip 16x. See "Column and Row Skip" on page 38 for more information. Row Skip When Read mode Context A is selected (Reg0xF2[3] = 0): Enable-- 1: Enable row skip. Context A 0: Normal readout. Row Skip-- When Read mode Context A is selected (Reg0xF2[3] = 0) and Context A Row skip is enabled (bit 4 = 1): "00"--Row Skip 2x. "01"--Row Skip 4x. "10"--Row Skip 8x. "11"--Row Skip 16x. See "Column and Row Skip" on page 38 for more information. Number of Dark Columns MT9D011 has 40 dark columns. 1: Read out 36 dark columns (4-39). Ignored during binning, where all 40 dark columns are used. 0: Read out 20 dark columns (4-23). Binning-- Context A DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 0 Y YM Bit 0 0 Y YM R33--0X21 - READ MODE--CONTEXT A (R/W) Bit 15 0 Y YM Bit 10 1 Y YM Bit 7 1 Y YM Bits 6:5 0 Y YM Bit 4 1 Y YM Bits 3:2 0 Y YM R34--0X22 - SHOW CONTROL (R/W) Bit 10 0 N N 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bit 9 Show Dark Columns Register Description (continued) DESCRIPTION When set, the 20/36 (dependent on bit 10) dark columns are output before the active pixels in a line. There is an idle period of two pixels between readout of the dark columns and readout of the active image. Therefore, when set, LINE_VALID is asserted 22 pixel times earlier than normal, and the horizontal blanking time is decreased by the same amount. 1: Enables the readout of dark columns for use in the rowwise noise correction algorithm. The number of columns used are 40 in binning mode, and otherwise determined by bit 10. 0: When disabled, an arbitrary number of dark columns can be read out by including them in the active image. Enabling the dark columns increases the minimum value for horizontal blanking but does not affect the row time. When set, the programmed dark rows is output before the active window. FRAME_VALID is thus asserted earlier than normal. This has no effect on integration time or frame rate. The start address for the dark rows within the eight available rows (an offset of four is added to compensate for the guard pixels). Must be set so all dark rows read out falls in the address space 0:7. Do not change from default value. A value of N causes (n+1) dark rows to be read out at the start of each frame when dark row readout is enabled (bit 3). Reflects the current state of the FLASH output pin. Indicates that the FLASH output pin is asserted for the current frame. Enable Xenon flash. When set, the FLASH output pin asserts for the programmed period (bits 7:0) during vertical blank. This is achieved by keeping the integration time equal to one frame, and the pulse width less than the vertical blank time. Delay of the flash pulse measured in frames. 1: In Xenon mode the flash is triggered after the resetting of a frame. 0: In Xenon mode the flash is triggered after the readout of a frame. 1: Flash should be enabled every frame. 0: Flash should be enabled for one frame only. Enable LED flash. When set, the FLASH output pin asserts prior to the start of the resetting of a frame and remains asserted until the end of the readout of the frame. DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 0 N N Bit 8 Read Dark Columns 1 N Y Bit 7 Show Dark Rows Dark Start Address 0 N N Bits 6:4 0 N N Bit 3 Bits 2:0 Reserved Num Dark Rows 7 N Y R35--0X23 - FLASH CONTROL (R/W) Bit 15 Bit 14 Bit 13 FLASH Triggered Xenon Flash 0 0 0 Y N1 Bits 12:11 Frame Delay Bit 10 End of Reset 0 1 N N N N Bit 9 Bit 8 Every Frame LED Flash 1 0 N Y N Y1 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bits 7:0 Xenon Count Register Description (continued) DESCRIPTION Length of FLASH pulse when Xenon flash is enabled. The value specifies the length in units of 1024*PIXCLK cycle increments. When the Xenon count is set to its maximum value (0xFF), the FLASH pulse is automatically truncated prior to the readout of the first row, giving the longest pulse possible. DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 8 N N R36--0X24 - EXTRA RESET (R/W) Bit 15 0: Only programmed window (set by Reg0x01 through Reg0x04) and black pixels are read. 1: Two additional rows are read and reset above and below programmed window to prevent blooming to active area. Next Row Reset When set, and the integration time is less than one frame time, row (n+1) is reset immediately prior to resetting row (n). This is intended to prevent blooming across rows under conditions of very high illumination. Reserved Do not change from default value. Xor LINE_VALID 1: LINE_VALID = "continuous" LINE_VALID XOR FRAME_VALID. 0: Normal LINE_VALID (default, no XORing of LINE_VALID). Ineffective if continuous LINE_VALID is set. 1: "Continuous" LINE_VALID (continue producing LINE_VALID during vertical blank). 0: Normal LINE_VALID (default, no LINE_VALID during vertical blank). The bottom dark rows are visible in the image if the bit is set. Defines the start address within the eight bottom dark rows. Enable readout of the bottom dark rows. Defines the number of bottom dark rows to be used. (The number of rows used is the specified value +1.) Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain (each bit gives 2x gain). Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit gives 2x gain). Initial gain = bits 6:0*0.03125. Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain (each bit gives 2x gain). Initial gain = bits [6:0]*0.03125. Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit gives 2x gain). Extra Reset Enable 1 N N Bit 14 0 N N Bits 13:0 Bit 15 R37--0X25 - LINE_VALID CONTROL (R/W) 0 N N Bit 14 Continuous LINE_VALID 0 N N3 R38--0X26 - BOTTOM DARK ROWS (R/W) Bit 7 Bits 6:4 Bit 3 Bits 2:0 Show Start Address Enable Readout Number of Dark Rows Digital Gain Analog Gain Initial Gain Digital Gain Initial Gain Analog Gain 0 0 0 7 N N N N N N Y Y R43--0X2B - GREEN1 GAIN (R/W) Bits 11:9 Bits 8:7 Bits 6:0 Bits 11:9 Bits 6:0 Bits 8:7 0 0 20 0 20 0 Y Y Y Y Y Y N N N N N N R44--0X2C - BLUE GAIN (R/W) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD R45--0X2D - RED GAIN (R/W) Bits 11:9 Bits 8:7 Bits 6:0 Bits 11:9 Bits 8:7 Bits 6:0 Bits 11:0 Digital Gain Analog Gain Initial Gain Digital Gain Analog Gain Initial Gain Global Gain Total gain = (bit 9 + 1)*(bit 10] + 1)*(bit 11 + 1)*analog gain (each bit gives 2x gain). Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit gives 2x gain). Initial gain = bits 6:0*0.03125. Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain (each bit gives 2x gain). Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit gives 2x gain). Initial gain = bits 6:0*0.03125. This register can be used to simultaneously set all four gains. When read, it returns the value stored in Reg0x2B. 0 0 20 0 0 20 20 Y Y Y Y Y Y Y N N N N N N N Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R46--0X2E - GREEN2 GAIN (R/W) R47--0X2F - GLOBAL GAIN (R/W) R48--0X30 - ROW NOISE (R/W) Bit 15 By default, the row noise is calculated and compensated for individually for each color of each row. When this bit is set, the row noise is calculated and applied for each color of each of the first two rows (two pairs of values) and the same values are applied to each subsequent row, so that new values are calculated and applied once per frame. Bits 14:12 Gain Threshold When the upper analog gain bits are equal to or larger than this threshold, the dark column average is used in the row noise correction algorithm. Otherwise, the subtracted value is determined by bit 11. This check is independently performed for each color, and is a means to turn off the black level algorithm for lower gains. Bit 11 Use Black Level 1: Use black level frame average from the dark rows in the Average row noise correction algorithm for low gains. Note: this frame average was taken before the last adjustment of the offset DAC for that frame, so it might be slightly off. 0: Use mean of black level programmed threshold in the row noise correction algorithm for low gains. Bit 10 Enable 1: Enable row noise cancellation algorithm. Correction When this bit is set, the average value of the dark columns read out is used as a correction for the whole row. The dark average is subtracted from each pixel on the row, and then a constant is added (bits 9:0). 0: Normal operation. Bits 9:0 Row Noise Constant used in the row noise cancellation algorithm. It Constant should be set to the dark level targeted by the black level algorithm plus the noise expected between the averaged values of the dark columns. The default constant is set to 42 LSB. Frame-wise Digital Correction 0 N N 0 N N 0 N Y 1 N Y 2A N Y 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD R89--0X59 - BLACK ROWS (R/W) Bits 7:0 Black Rows For each bit set, the corresponding dark row (rows 0-7) are used in the black level algorithm. For this to occur, the reading of those rows must be enabled by the settings in Reg0x22. The frame-averaged green1 black level that is used in the black level calibration algorithm. The frame-averaged blue black level that is used in the black level calibration algorithm. The frame-averaged red black level that is used in the black level calibration algorithm. The frame-averaged green2 black level that is used in the black level calibration algorithm. Upper threshold for targeted black level in ADC LSBs. Lower threshold for targeted black level in ADC LSBs. 23 1D N N N N FF N N Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R91--0X5B - GREEN1 FRAME AVERAGE (R/O) Bits 6:0 Green1 Frame Average Blue Frame Average Red Frame Average Green2 Frame Average Upper Threshold Lower Threshold Disable Rapid Sweep Mode Recalculate R92--0X5C - BLUE FRAME AVERAGE (R/O) Bits 6:0 R93--0X5D - RED FRAME AVERAGE (R/O) Bits 6:0 R94--0X5E - GREEN2 FRAME AVERAGE (R/O) Bits 6:0 R95--0X5F - THRESHOLD (R/W) Bits 14:8 Bits 6:0 R96--0X60 - CALIBRATION CONTROL (R/W) Bit 15 Bit 12 Disables the rapid sweep mode in the black level algorithm. The averaging mode remains enabled. When set, the rapid sweep mode is triggered if enabled, and the running frame average is reset to the current frame average. This bit is write-1, but always reads back as 0. 1: Dark rows 8-11 are not used for the black level algorithm controlling the calibration value. Instead, these rows are used to calculate dark averages that can be a starting point for the digital frame-wise black level algorithm. 0: All dark rows can be used for the black level algorithm. This means that the internal average might not correspond to the calibration value used for the frame, so the dark row average should in this case not be used as the starting point for the frame-wise black level algorithm. When set, does not let the averaging mode of the black level algorithm change the calibration value. Use this with the feature in the frame-wise black level algorithm that allows you to trigger the rapid sweep mode when the dark column average gets away from the black level target. When set, the calibration value is increased by one every frame, and all channels are the same. This can be used to get a ramp input to the ADC from the calibration DACs. 0 0 Y Y N N Bit 10 Limit Rapid Sweep 0 N N Bit 9 Freeze Calibration 0 N N Bit 8 Sweep Mode 0 N N 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Bits 7:5 Frames To Average Over Register Description (continued) DESCRIPTION Two to the power of this value determines how many frames to average when the black level algorithm is in the averaging mode. In this mode, the running frame average is calculated from the following formula: Running frame ave = old running frame ave (old running frame ave)/2n + (new frame ave)/ 2n. Step Size When set, the step size is forced to 1 for the rapid sweep Forced To 1 algorithm. Default operation (0) is to start at a higher step size when in rapid sweep mode, to converge faster to the correct value. Switch When set, the calibration values applied to the two channels Calibration are switched. This is not recommended and should not be Values used. Same Red/Blue When this bit is set, the same calibration value is used for red and blue pixels: Calib blue = calib red. Same Green When this bit is set, the same calibration value is used for all green pixels: Calib green2 = calib green1. Manual Manual override of black level correction. Override 1: Override automatic black level correction with programmed values. (Reg0x61-Reg0x64). 0: Normal operation (default). Green1 Calibration Value Analog calibration offset for green1 pixels, represented as a two's complement signed 8-bit value (if bit 8 is clear, the offset is positive and the magnitude is given by bits 7:0. If bit 8 is set, the offset is negative and the magnitude is given by not ([7:0]) + 1). If Reg0x60[0] = 0, this register is R/O and returns the current value computed by the black level calibration algorithm. If Reg0x60[0] = 1, this register is R/W and can be used to set the calibration offset manually. Green1 pixels share rows with red pixels. Analog calibration offset for blue pixels, represented as a two's complement signed 8-bit value (if bit 8 is clear, the offset is positive and the magnitude is given by bits 7:0. If bit 8 is set, the offset is negative and the magnitude is given by not ([7:0]) + 1). If Reg0x60[0] = 0, this register is R/O and returns the current value computed by the black level calibration algorithm. If Reg0x60[0] = 1, this register is R/W and can be used to set the calibration offset manually. DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME 4 N N Bit 4 0 N N Bit 3 0 Bit 2 Bit 1 Bit 0 0 0 0 N N N Y Y Y R97--0X61 - GREEN1 CALIBRATION VALUE (R/W) Bits 8:0 0 N Y R98--X62 - BLUE CALIBRATION VALUE (R/W) Bits 8:0 Blue Calibration Value 0 N Y R99--0X63 - RED CALIBRATION VALUE (R/W) Bits 8:0 Red Calibration Analog calibration offset for red pixels, represented as a Value two's complement signed 8-bit value (if bit 8 is clear, the offset is positive and the magnitude is given by bits 7:0. If bit 8 is set, the offset is negative and the magnitude is given by not([7:0]) + 1). If Reg0x60[0] = 0, this register is R/O and returns the current value computed by the black level calibration algorithm. If Reg0x60[0] = 1, this register is R/W and can be used to manually set the calibration offset. 0 N Y 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R100--0X64 - GREEN2 CALIBRATION VALUE (R/W) Bits 8:0 Green2 Calibration Value Analog calibration offset for green2 pixels, represented as a two's complement signed 8-bit value (if bit 8 is clear, the offset is positive and the magnitude is given by bits 7:0. If bit 8 is set, the offset is negative and the magnitude is given by not ([7:0]) + 1.) If Reg0x60[0] = 0, this register is R/O and returns the current value computed by the black level calibration algorithm. If Reg0x60[0] = 1, this register is R/W and can be used to manually set the calibration offset. Green2 pixels share rows with blue pixels. 1: Bypass the PLL. Use CLKIN port as master clock. 0: Use clock produced by PLL as master clock. 1: Keep PLL in power-down to save power (default). 0: PLL powered-up. This register only has an effect when bit 14 = 0. 1: Turn off PLL (power-down) during Standby to save power (default). 0: PLL powered-up during Standby. Force clk_newrow to be on continuously. Force clk_newframe to be on continuously. Force clk_ship to be on continuously. M value for PLL must be 16 or higher. N value for PLL. Do not change from default value. P value for PLL. Enter global reset. Alternative to using GRST_CTR pin. This bit is write -1 only and is always read 0. 1: Flash is de-asserted at end of readout. 0: Flash is de-asserted by Reg0xB6 (de-assert flash). 1: Strobe is de-asserted at end of readout. 0: Strobe is de-asserted by Reg0xC4 (de-assert strobe). 1: Start of readout is controlled by falling edge of GRST_CTR pin. 0: Start of readout is controlled by Reg0xC2 (start readout time). These 16 bits are compared to the upper bits of a 24-bit counter, which starts counting master clocks when global reset starts. When this value is reached, global reset is deasserted, and integration time starts. Note: there is a minimum time period for which global reset is always held. This time is defined by the physical properties of the boost circuit. 0 N Y R101--0X65 - CLOCK (R/W) Bit 15 Bit 14 Bit 13 PLL Bypass PLL Powerdown Power-down PLL During Standby clk_newrow clk_newframe clk_ship M N Reserved P Global Reset Enable Global Reset Flash Control Global Reset Strobe Control Global Reset Readout Control 1 1 1 N N N N N N Bit 2 Bit 1 Bit 0 Bits 15:8 Bits 5:0 Bits 11:8 Bits 6:0 Bit 15 Bit 2 Bit 1 Bit 0 0 0 0 28 9 N N N N N N N N N N R102--0X66 - PLL CONTROL 1 (R/W) R103--0X67 - PLL CONTROL 2 (R/W) 1 0 0 0 0 N N N N N N N4 N N N R192--0XC0 - GLOBAL RESET CONTROL (R/W) R193--0XC1 - START INTEGRATION TIME (T1) (R/W) Bits 15:0 Start Integration Time (T1) 64 N N 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R194--0XC2 (194) START READOUT TIME (T2) (R/W) Bits 15:0 Start Readout Time (T2) These 16 bits are added to Reg0xC1 (start integration time) and compared to the 24-bit counter mentioned for Reg0xC1. The value defines the time from when integration time starts to when it is guaranteed to end. Readout then commences. These 16 bits are compared to the upper bits of a 24-bit counter, which starts counting master clocks when global reset starts. When this value is reached, the strobe is asserted. These 16 bits are compared to the upper bits of a 24-bit counter, which starts counting master clocks when global reset starts. When this value is reached, the strobe is deasserted if strobe control is 0 (Reg0xC0[1]). These 16 bits are compared to the upper bits of a 24-bit counter, which starts counting master clocks when global reset starts. When this value is reached, the flash is asserted. 64 N N R195--0XC3 - ASSERT STROBE TIME (T3) (R/W) Bits 15:0 Assert Strobe Time (T3) 96 N N R196--0XC4 - DE-ASSERT STROBE TIME (T4) (R/W) Bits 15:0 De-assert Strobe Time (T4) C8 N N R197--0XC5 - ASSERT FLASH TIME (R/W) Bits 15:0 Assert Flash Time 64 N N R198--0XC6 - DE-ASSERT FLASH TIME (R/W) Bits 15:0 De-assert Flash These 16 bits are compared to the upper bits of a 24-bit Time counter, which starts counting master clocks when global reset starts. When this value is reached, the flash is deasserted if flash control is 0 (Reg0xC0[2]). External Sampling 3 Contains sample of AIN3 if external sampling is enabled (Reg0xE3[15] = 1). See "Analog Inputs AIN1-AIN3" on page 54. Contains sample of AIN2 if external sampling is enabled (Reg0xE3[15] = 1). Contains sample of AIN1 if external sampling is enabled (Reg0xE3[15] = 1). 1: Enable external sampling. 0: Disable external sampling. If external sampling is enabled (Reg0xE3[15] = 1): 1: Show the external samples in the data stream after LINE_VALID goes low. 0: Don't show external samples in data stream. Must be 0. 0 0 N N N N 78 N N R224--0XE0 - EXTERNAL SAMPLING 3 (R/O) Bits 9:0 R225--0XE1 - EXTERNAL SAMPLING 2 (R/O) Bits 9:0 External Sampling 2 External Sampling 1 Enable Sampling Show Sample R226--0XE2 - EXTERNAL SAMPLING 1 (R/O) Bits 9:0 R227--0XE3 - EXTERNAL SAMPLING CONTROL (R/W) Bit 15 Bit 14 R240--0XF0 - PAGE REGISTER (R/W) Bits 2:0 Page Register 0 N N 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 7: BIT FIELD Register Description (continued) DESCRIPTION DEFAULT SYNC'D TO BAD (HEX) FRAME START FRAME R241--0XF1 - BYTEWISE ADDRESS (R/W) Bits 15:0 Bytewise Address Special address to perform 16-bit reads and writes to the sensor in 8-bit chunks. See "8-Bit Write Sequence" on page 15. Setting this bit causes the sensor to abandon the current frame and start resetting the first row. Same physical register as Reg0x0D[1]. Enable Xenon flash. Same physical register as Reg0x23[13]. 1: Use Read mode Context B, Reg0x20. 0: Use Read mode Context A, Reg0x21. Note that bits only found in Read mode Context B register are always taken from that register. Enable LED flash. Same physical register as Reg0x23[8]. 1: Use Vertical Blank Context B, Reg0x06. 0: Use Vertical Blank Context A, Reg0x08. 1: Use Horizontal Blank Context B, Reg0x05. 0: Use Horizontal Blank Context A, Reg0x07. Chip version. 0 N N R242--0XF2 - CONTEXT CONTROL (R/W) Bit 15 Restart 0 N YM Bit 7 Bit 3 Xenon Flash Enable Read Mode Select 0 1 Y Y N YM Bit 2 Bit 1 Bit 0 LED Flash Enable Vertical Blank Select Horizontal Blank Select Chip Version 0 1 1 Y Y Y Y YM YM R255--0XFF - CHIP VERSION (R/O) Bits 15:0 NOTE: 1511 "Flash STROBE" on page 48. integration time is less than one frame. 3If enabled in bit 3. 4Will cause current frame to stop if triggered during a frame. Notation used in the register description table: Sync'd to frame start N = No. The register value is updated and used immediately. Y = Yes. The register value is updated at next frame start as long as the synchronize changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default, this is 8 rows before FRAME_VALID goes HIGH. Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. N = No. Changing the register value does not produce a bad frame. Y = Yes. Changing the register value might produce a bad frame. YM = Yes, but the bad frame is masked out unless the "show bad frames" feature is enabled. 2Unless 1See 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Feature Description PLL Generated Master Clock The MT9D011 has an on-chip PLL that can generate a master clock in the range of 36 MHz to 40 MHz from an input reference clock of 4 MHz to 40 MHz. It is possible to bypass the PLL and use CLKIN as master clock. This is controlled by Reg0x65[15]. When the PLL is bypassed (Reg0x65[15] = 1), it is recommended to set the PLL in power down mode by setting Reg0x65[14] = 1. Default mode is PLL bypassed and in powerdown mode. Reg0x66 and Reg0x67 controls the frequency setting of the generated clock. PLL Settings The PLL is controlled through its M, N and P parameters, as set in registers 0x66 and 0x67. The PLL output frequency (fout) has the following relationship to the input frequency (fin): fout = fin*M/(2*(N+1)*(P+1)) Not all possible settings are allowed. M must be 16 or higher. Also, the following restrictions on frequencies must be obeyed: 2. Power up PLL (Reg0x65[14] = 0) 3. Wait for PLL settling time > 150s 4. Turn off PLL bypass (Reg0x65[15] = 0) Window Control Window Start The row and column start address of the displayed image can be set by Reg0x01 (Row Start) and Reg0x02 (Column Start). Window Size The size of the displayed image can be set by Row Width Reg0x03 and Column Width Reg0x04. The default image size is 1600 columns and 1200 rows (UXGA). The window start and size registers can be used to configure an image size between 17 and 1632 columns and between 2 and 1216 rows. Pixel Border When Reg0x20[9:8] are both set, a four pixel border is added around the specified image. This border can be used as extra pixels for image processing algorithms. The border is independent of the readout mode, which means that even in skip, zoom, and binning modes, a four pixel border is output in the image. When enabled, the row and column widths are eight pixels larger than the values programmed in Reg0x03 and Reg0x04. If the border is enabled but not shown in the image (Rex0x20[9:8] = 01), the horizontal blanking and vertical blanking values are eight pixels larger than the values programmed in the blanking registers. FREQUENCY EQUATION MIN [MHZ] fin/(N+1) 2 fPFD fPFD*M 110 fVCO fVCO/(2*(P+1) 36 fout MAX [MHZ] 16 220 40 PLL Power-up The PLL takes time to power up. During this time, the behavior of its output clock is not guaranteed. The PLL is in power-down by default and must be turned on manually. When using the PLL, the correct powerup sequence after chip reset is as follows: 1. Program PLL frequency settings (Reg0x66 and Reg0x67) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Readout Modes Readout Speeds and Power Savings The MT9D011 has two ADCs to convert the pixel values to digital data. Because the ADCs run at half the master clock frequency, it is possible to achieve a data rate equal to the master clock frequency. By turning off one of the ADCs, the power consumption of the sensor is reduced. The pixel clock is then reduced by a factor of two. In Reg0x20 or Reg0x21, bit 10 chooses between the two modes: 0: Use both ADCs and read out at the set pixel clock frequency (Reg0x0A, bits 3:0). 1: Use 1 ADC and read out at half the set pixel clock frequency (Reg0x0A, bits 3:0). This can be used, for instance, when the camera is in preview mode. To make the transitions between two sensor settings easier, some simple context switching is described in "Context Switching" on page 44. Column Mirror Image By setting Reg0x20[1] = 1 (Reg0x21 in Context A), the readout order of the columns are reversed as shown in Figure 13. The starting color is preserved when mirroring the columns. Row Mirror Image By setting Reg0x20[0] = 1 (Reg0x21 in Context A), the readout order of the rows are reversed as shown in Figure 14. The starting color is preserved when mirroring the rows. Figure 13: Six Pixels in Normal and Column Mirror Readout Modes LINE_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 G3 (9:0) R2 (9:0) G2 (9:0) R1 (9:0) G1 (9:0) R0 (9:0) G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) Figure 14: Six Rows in Normal and Row Mirror Readout Modes FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Row6 (9:0) Row5 (9:0) Row4 (9:0) Row3 (9:0) Row2 (9:0) Row1 (9:0) Row0 (9:0) Row1 (9:0) Row2 (9:0) Row3 (9:0) Row4 (9:0) Row5 (9:0) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Column and Row Skip This section assumes Context B. If Context A is used, replace all references to Reg0x20 with Reg0x21. By setting Reg0x20[4] = 1 or Reg0x20[7] = 1, skip is enabled for rows or columns, respectively. When skip is enabled, the image is subsampled. The amount of skipping is set by Reg0x20[3:2] (rows) and Reg0x20[6:5] (columns) according to Table 8. The number of rows or columns read out is what is set in Reg0x03 or Reg0x04, respectively, divided by the Skip Value in this table. In all cases, the row and column sequencing ensures that the Bayer pattern is preserved. Column skip examples are shown in Figures 15 through 18. Table 8: 00 01 10 11 Skip Values SKIP VALUE 2 4 8 16 BIT VALUES Figure 15: Eight Pixels in Normal and Column Skip 2x Readout Modes LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) G3 (9:0) R3 (9:0) LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G2 (9:0) R2 (9:0) Figure 16: Sixteen Pixels in Normal and Column Skip 4x Readout Modes LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) G7 (9:0) R7 (9:0) LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G4 (9:0) R4 (9:0) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 17: Thirty-two Pixels in Normal and Column Skip 8x Readout Modes LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) G15 (9:0) R15 (9:0) LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G8 (9:0) R8 (9:0) Figure 18: Sixty-four Pixels in Normal and Column Skip 16x Readout Modes LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) G31 (9:0) R31 (9:0) LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G16 (9:0) R16 (9:0) Digital Zoom Reg0x20[13] enables a digital zoom of 2x to 16x to be applied. The zoom value is set in Reg0x20[12:11] according to Table 9. In zoom mode, the pixel data rate is slowed by the zoom factor, and a number of additional blank rows are added between output rows (see Table 9). This is designed to give the controller logic the necessary time to repeat data, filling in a larger window with repeated data. Table 9: BIT VALUES 00 01 10 11 Zoom Values ZOOM VALUE 2 4 8 16 BLANK ROWS 1 3 7 15 The pixel clock speed is not affected by this operation, therefore the output data for each pixel is valid for zoom factor number of pixel clocks. Every row is followed by a number of blank rows (with their own LINE_VALID, but all data bits = 0) of equal time. In zoom modes, Reg0x03 and Reg0x04 still specifies the window size out of the sensor including the extra blanking, so the active image read out is, in effect, smaller than the output image. Figures 19 through 23 show the data coming from the sensor in the different zoom modes. The colors represent from which colored pixel the data comes. Black represents data = 0. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 19: Data from Pixel Array in Normal Mode A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 J0 J1 J2 J3 J4 J5 J6 J7 J8 J9 Figure 20: Data from Pixel Array in Zoom 2x Mode A0 B0 C0 D0 E0 F0 G0 H0 I0 J0 A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 A2 B2 C2 D2 E2 F2 G2 H2 I2 J2 A3 B3 C3 D3 E3 F3 G3 H3 I3 J3 A4 B4 C4 D4 E4 F4 G4 H4 I4 J4 A5 B5 C5 D5 E5 F5 G5 H5 I5 J5 A6 B6 C6 D6 E6 F6 G6 H6 I6 J6 A7 B7 C7 D7 E7 F7 G7 H7 I7 J7 A8 B8 C8 D8 E8 F8 G8 H8 I8 J8 A9 B9 C9 D9 E9 F9 G9 H9 I9 J9 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 21: Data from Pixel Array in Zoom 4x Mode A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 E0 E1 E2 E3 E4 E5 E6 E7 F0 F1 F2 F3 F4 F5 F6 F7 G0 G1 G2 G3 G4 G5 G6 G7 H0 H1 H2 H3 H4 H5 H6 H7 Figure 22: Data from Pixel Array in Zoom 8x Mode A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 23: Data from Pixel Array in Zoom 16x Mode A0 A1 B0 B1 Binning The MT9D011 supports 2 x 2 binning of four pixels of the same color. This mode can be activated by asserting Reg0x20[15] (Reg0x21 if Context A is used). Binning is primarily used instead of 2x skip as a way of decimating the picture without losing information. The effect of aliasing in preview mode is eliminated when binning is used instead of just skipping rows and columns. Activating binning has several implications. * It adds a level of skip, so the picture that comes out has the same dimensions as a picture read out with the next higher skip setting. * It increases the minimum hblank and minimum row time requirements (see Table 10 and Table 11). Binning Limitations To achieve correct operation, the following conditions must be met: * Start address must be divisible by four (row and column). * Window size must be divisible by four in both directions, after dividing by zoom factor and skip factor (because they both reduce the effective window size from the sensor's point of view). Example: Default row size = 1200. 8x zoom means the actual window on the sensor is divided by 8, so 8x zoom and binning is not allowed with default window size, because 1200 / 8 = 150, which is not divisible by 4. * Binning can be seen as an extra level of skip. The combination binning/16x skip is therefore not legal. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Frame Rate Control For a given window size, the blanking registers (Reg0x05-Reg0x08) along with the row speed register (Reg0x0A) can be used to set a particular frame rate. The frame timing equations (Table 3 and Table 4 on page 12) can be rearranged to express the horizontal blanking or vertical blanking values as a function of the frame rate: HBLANK_REG = master clock freq / (frame rate* ((Reg0x03/S + BORDER) + VBLANK_REG)*PIXCLK_PERIOD) - (Reg0x04/S + BORDER) VBLANK_REG = master clock freq / (frame rate* ((Reg0x04/S + BORDER) + HBLANK_REG)*PIXCLK_PERIOD) - (Reg0x03/S + BORDER) The HBLANK_REG value allows the frame rate to be adjusted with a minimum resolution of one PIXCLK_PERIOD multiplied by the total number of rows (displayed plus blanking). When finer resolution is required, Reg0x0b (Extra Delay) can be used. Reg0x0b allows the frame time to be changed in increments of pixel clocks. Minimum Horizontal Blanking The minimum horizontal blanking value is constrained by the time used for sampling a row of pixels and the overhead in the row readout. This is expressed in Table 10. Table 10: Minimum Horizontal Blanking Parameters PARAMETER HBLANK(MIN) DEFAULT / 2 ADC MODE, 1 ADC MODE, 2 ADC MODE, 1 ADC MODE, NO BINNING NO BINNING BINNING BINNING 286 mclks 324 mclks = 162 pixclks 470 mclks 508 mclks = 254 pixclks Minimum Row Time Requirement The total row time must be sufficient to allow all row operations (readout and shutter operations). The row time is the sum of column width (halved during binning divided by column skip factor) and horizontal blanking, and can therefore be adjusted by programming these. Table 11 shows minimum row time as a function of mode of operation. Note that this is a particularly strict requirement during binning because twice as many row operations are required per row and the column width is halved. Table 11: Minimum Row Time Parameters PARAMETER ROW_TIME(MIN) DEFAULT / 2 ADC MODE, 1 ADC MODE, 2 ADC MODE, 1 ADC MODE, NO BINNING NO BINNING BINNING BINNING 473 mclks 488 mclks = 244 pixclks 464 mclks 931 mclks 919 mclks 946 mclks = 473 pixclks 922 mclks pointer_operations 461 mclks 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Context Switching Reg0xF2 is designed to enable easy switching between sensor modes. Some key registers and bits in the sensor have two physical register locations, called contexts. Bits 0, 1, and 3 of Reg0xF2 control which context register context is currently in use. A "1" in a bit selects Context B, while a "0" selects Context A for this parameter. The select bits can be used in any combination, but by default are setup to allow easy switching between preview mode and full resolution mode: CONTEXT B (DEFAULT CONTEXT) Reg0xF2 Reg0x05 Reg0x06 Reg0x20 = 0x000B = 0x015C = 0x0020 = 0x0000 (Context B) (Horizontal Blanking, Context B) (Vertical Blanking, Context B) (2 ADCs, no column or row skip) DESCRIPTION: Full-resolution UXGA (1600 x 1200) image at 15 fps CONTEXT A (ALTERNATE CONTEXT, PREVIEW MODE) Reg0xF2 Reg0x07 Reg0x08 Reg0x21 = 0x0000 = 0x00AE = 0x0010 = 0x0490 (Context A) (Horizontal blanking, Context A) (Vertical blanking, Context A) (1 ADC, 2x column and row skip) DESCRIPTION: Half-resolution SVGA (800 x 600) image at 30 fps The horizontal blanking and vertical blanking values for the two contexts are chosen so that row time is preserved between contexts. This ensures that changing contexts does not affect integration time. A few more control bits are also available through the context register (Reg0xF2) so that flash and restarting the sensor can be done simultaneously with changing contexts. See Table 7 on page 22 for more information. Settings for skip, 1 ADC mode, and binning can be set separately for Context B and Context A using Reg0x20 and Reg0x21, respectively. When these settings are referred to in this document, the register is dependent on what context is set in Reg0xF2. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Valid Data Signals Options LINE_VALID Signal By setting bits 14-15 of Reg0x25, the LINE_VALID signal is programmed for three different output formats. The formats shown in Figure 24 illustrate reading out four rows and two vertical blanking rows. In the last format, the LINE_VALID signal is the XOR between the continuous LINE_VALID signal and the FRAME_VALID signal. Figure 24: LINE_VALID Formats Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID FRAME_VALID Signal Reg0x1F allows the user to move FRAME_VALID with respect to data (and LINE_VALID). The rising and falling edges of FRAME_VALID are separately programmable, and can be moved earlier by a number of row_times (plus some overhead). By programming a value of N in bits [6:0] and enabling it in bit 7, FRAME_VALID will rise before the horizontal blanking N+1 rows earlier. This is shown in Figure 25. N should not be set to higher than 9. Similarly, by programming a value of M in bits [14:8] and enabling it in bit 15, FRAME_VALID will fall M+1 rows earlier. This is shown in Figure 26. M must not be set so FRAME_VALID would fall before LINE_VALID starts toggling. This is avoided by keeping M smaller than Row Width (Reg0x03/S + BORDER). 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 25: Early FRAME_VALID Rise LINE_VALID FRAME_VALID--normal FRAME_VALID--early fall = 0 FRAME_VALID--early fall = 1 FRAME_VALID--early fall = 5 Figure 26: Early FRAME_VALID Fall LINE_VALID FRAME_VALID--normal FRAME_VALID--early fall = 0 FRAME_VALID--early fall = 1 FRAME_VALID--early fall = 5 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Integration Time Integration time is controlled by Reg0x09 (shutter width in multiples of the row time) and Reg0x0C (shutter delay, in PIXCLK_PERIOD/2). Reg0x0C is used to control sub-row integration times and only has a visible effect for small values of Reg0x09. The total integration time, tINT, is shown in the equation below: t INT = Reg0x09*Row Time - Integration Overhead - Shutter Delay where: Row Time = (Reg0x04/S + BORDER + HBLANK_REG)*PIXCLK_PERIOD master clock periods (from Table 3 on page 12) S = Skip Factor, multiplied by 2 if binning is enabled Overhead Time = 260 master clock periods (262 in 1 ADC mode) Shutter Delay = Reg0x0C*PIXCLK_PERIOD master clock periods (/2 in 1 ADC mode) with default settings: tINT = (1232*(1600 + 348)) - 260 - 0 = 2,399,676 master clock periods = 66.66ms@36 MHz In the equation, the Integration Overhead corresponds to the delay between the row reset sequence and the row sample (read) sequence. Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), so that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the sensor adds blanking rows as needed. Additionally, tINT must be adjusted to avoid banding in the image caused by light flicker. Therefore, tINT must be a multiple of 1/120 of a second under 60Hz flicker, and a multiple of 1/100 of a second under 50Hz flicker. Maximum Shutter Delay The shutter delay can be used to reduce the integration time. A programmed value of N reduces the integration time by N master clock periods. The maximum shutter delay is set by the row time and the sample time, as shown in the equation below: Maximum shutter delay = (Row Time - pointer_operations) where: Row Time = (Reg0x04/S + BORDER + HBLANK_REG)*PIXCLK_PERIOD master clock periods (from Table 3 on page 12) S = Skip Factor, multiplied by 2 if binning is enabled pointer_operations = see Table 11 on page 43. with default settings: Maximum shutter delay = (1600 + 348) - 461 = 1487 (master clock periods) If the value in this register exceeds the maximum value given by this equation, the sensor may not generate an image. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Flash STROBE The MT9D011 supports both Xenon and LED flash through the FLASH output pin. The timing of the FLASH pin with the default settings is shown in Figure Figure 27, Figure 28, and Figure 29. Reg0x23 allows the timing of the flash to be changed. The flash can be programmed to: fire only once; be delayed by a few frames when asserted; and (for Xenon flash) the flash duration can be programmed. When Xenon flash is enabled, an integration time significantly smaller than one frame will cause uneven exposure of the image, as will setting a flash pulse width larger than Vertical Blanking. Enabling the LED flash causes one bad frame in which several rows have the flash on during only part of their integration time. This can be avoided by forcing a restart (write Reg0x0D[1] = 1) immediately after enabling the flash; the first bad frame is then masked out as shown in Figure 29. Read-only bit Reg0x23[14] is set during frames that are correctly integrated; the state of this bit is shown below. Figure 27: Xenon Flash Enabled FRAME_VALID Flash STROBE Figure 28: LED Flash Enabled FRAME_VALID Flash STROBE Flash enabled during this frame NOTE: Bad frame Bad frame Good frame Good frame Flash disabled during this frame Integration time = number of rows in a frame. Figure 29: LED Flash Enabled, Using Restart FRAME_VALID Flash STROBE Flash enabled and a restart triggered NOTE: Masked out frame Masked out frame Good frame Good frame Flash disabled and a restart triggered Integration time = number of rows in a frame. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Global Reset The MT9D011 provides a global reset mode in which the pixel integration time is controlled by an external mechanical shutter. The sensor can then operate on a lower clock frequency, reducing the bandwidth on the interface between the sensor and the host processor without losing image quality. The basic operation is as follows: The sensor operates in either preview or full-frame mode (Electronic Rolling Shutter or ERS). A rising edge on the signal GRST_CTR or a write to an internal register starts the global reset sequence. The sensor now enters the snapshot mode and after a certain time, all the lines in the sensor array is reset and kept in a reset state until the integration starts. The start of the integration (exposure) period, the assertion of the STROBE signal, the start of the readout and the de-assertion of the STROBE signal can be controlled by internal registers (T1, T2, T3 and T4 shown in Figure 30). The MT9D011 provides an output signal, STROBE, that can be used to control the mechanical shutter. This signal can be programmed to occur in a specified window around the actual start of integration. During Global Reset, the FLASH pin is programmed in a different way than during normal ERS operation. Normally, the FLASH behavior is programmed using Reg0x23. In Global Reset mode, the FLASH strobe is programmed in the same way as the STROBE pin showed in Figure 30, using registers Reg0xC5 and Reg0xC6. Reg0xC0[0] controls the mechanism for starting the readout after a global reset operation. If this bit is high, the integration time is directly controlled by the GRST_CTR pin. Very long integration times can be achieved this way. Figure 30: Global Reset Operation Global Reset Complete Integration Starts Readout Can Start GRST_CTR T1 T3 T4 STROBE T2 ERS Mode ERS m od Snapshot Mode Reset Pixel Array Wait Integration until shutter close Readout Frame ERS Mode 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Analog Signal Path The MT9D011 features two identical analog readout channels. A block diagram for one channel is shown in Figure 31. The readout channel consists of two gain stages (ASC1 and ASC2), a sample-and-hold (ADCSH) stage with black level calibration capability (VOFFSET), and a 10-bit ADC. Figure 31: Analog Readout Channel V1 Vpix ASC1 (G1) ASC2 (G2) V2 V3 ADCSH (G3) VREFD 10-bit ADC ADC_code 10 + VOFFSET Stage-by-Stage Transfer Functions Transfer functions proceed stage-by-stage, as follows: Let VPIX be the input of the signal path: The output voltage of ASC 1st stage is: The output voltage of ASC 2nd stage is: The output voltage of ADC Sample-and-Hold stage is: and the ADC output code is: VPIX = pixel output voltage = signal path input voltage, V1 = -1*G1*VPIX V2 = -1*G2*V1 V3 = 2*G3*V2 - VREFD + VOFFSET ADC output code = 511*(1 + (V3 / VrEFD)) (1) (2) (3) (4) (5) From (1) to (4), the ADC output code can also be written as: ADC code = (1022/VREFD)*[G1*G2*G3*VPIX + (Voffset/(2*G3))] Where G1, G2, and G3 are the gain settings, VOFFSET is the offset (calibration) voltage, and VREFD is the reference voltage of the ADC. The gain setting G3 is applied to the signal but is not applied to VOFFSET. The parameters VREFD, G1, G2, G3, and VOFFSET are described next. VREFD The VREFD parameters are as follows: The ADC reference voltage VREFD Is: VREFD = VREF_HI - VREF_LO where using default register values: and using default register values: so using default register values VREF_HI = 55.5mV*(Reg0x41[7:4] + 23) VREF_HI = 55.5mV*(13 + 23) = 1.998V VREF_LO = 55.5mV*(Reg0x41[3:0] +11) VREF_LO = 55.5mV*(7 +11) = 0.999V VREFD = 55.5mV*(Reg0x41[7:4] - Reg0x41[3:0] + 12) VREFD = 1.998 - 0.999 = 0.999V (9) (8) (6) (7) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Gain Settings: G1, G2, G3 The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be globally set by Reg0x2F. The analog gain is set by bits 8:0 of the corresponding register as follows: G1 = bit 7 + 1 G2 = bit 6:0 / 32 G3 = bit 8 + 1 (10) (11) (12) 01 "Offset_gain" is determined by the 2-bit code from Reg0x5A[1:0], as shown in Table 12. These step sizes are not exact; increasing the stage0 ADC gain from 2 to 4 decreases the step size significance; decreasing the ADC VREFD increases the step size significance. Table 12: Offset Gain REG0X5A[1:0] 00 OFFSET_GAIN OFFSET_GAIN = 0 (no calibration voltage is applied) OFFSET_GAIN = 0.25 (1 calibration LSB is equal to 0.5 ADC LSB when VREFD = 1V) OFFSET_GAIN = 0.50 (1 calibration LSB is equal to 1 ADC LSB when VREFD = 1V) OFFSET_GAIN = 1 (1 calibration LSB is equal to 2 ADC LSB when VREFD = 1V) Digital gain is set by bits 11:9 of the same registers. Offset Voltage: VOFFSET The offset voltage provides a constant offset to the ADC to fully utilize the ADC input dynamic range. The offset voltages for green1, blue, red, and green2 pixels are manually set by registers Reg0x61, Reg0x62, Reg0x63, and Reg0x64, respectively. Note that the offset voltages also can be automatically set by the blacklevel calibration loop. For a given color, the offset voltage, VOFFSET, is determined by: (13) VOFFSET = 0.50V*offset_gain*offset_sign*offset_code[7: 0]/255 where: "offset_sign" is determined by bit 8 as: if bit 8 = 0, offset_sign = +1 if bit 8 = 1, offset_sign = -1 "offset_code" is the decimal value of bit<7:0> (14) (15) 10 11 Recommended Gain Settings The analog gain circuitry in the MT9D011 provides signal gains from 1 to 15.875. Table 13: Recommended Gain Settings DESIRED GAIN 1-1.969 2-7.938 8-15.875 RECOMMENDED GAIN REGISTER SETTING 0x020-0x03F 0x0A0-0x0FF 0x1C0-0x1FF Output Enable Control When the sensor is configured to operate in Default mode, the DOUT, FRAME_VALID, LINE_VALID, PIXCLK, and flash outputs can be placed in a high-impedance state under hardware or software control, as shown in Table 14. Table 14: Output-Enable Control STANDBY 0 1 don't care don't care REG0X0D[4] (OUTPUT_DIS) 0 (default) 0 (default) 0 (default) 1 REG0X0D[6] (DRIVE_PINS) 0 (default) 0 (default) 1 don't care PIN STATE Driven High-Z Driven High-Z The pin transition between driven and High-Z always occurs asynchronously. Output-enable control is provided as a mechanism to allow multiple sensors to share a single set of interface pins with a host controller. NOTE: There is no benefit in placing the pins in a High-Z while the sensor is in its low power standby state. Therefore, in single-sensor applications that use the STANDBY pin to 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR enter and leave the standby state, programming Reg0x0D[6] = 1 is recommended. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Power-Saving Modes The sensor can be placed in a low power standby state by either of these mechanisms: * Asserting STANDBY input pin (provided that Reg0x0D[7] = 0) * Setting Reg0x0D[2] = 1 by performing a register write through the serial register interface. These two methods are equivalent and have the same effect: * The source of standby is synchronized and latched. Once latched, the full standby sequence is completed even if the source of standby is removed. * The readout of the current row is completed. * Internal clocks are gated off. * The analog signal chain and associated current and voltage sources are placed in a low power state. The standby state is maintained for as long as the standby source remains asserted. Table 15 shows the state of the pin interface while in standby state. PLL and Standby If the PLL is used to generate master clock, special care must be taken when entering standby mode. The PLL uses relatively high power, so allowing the PLL to power down during standby is recommended. This can be controlled in Reg0x65[13]. By default the PLL powers down whenever MT9D011 enters standby. The operation of the circuit cannot be guaranteed if the PLL is driving the master clock when it powers down. To safely allow the PLL to power down when entering standby, turn on PLL bypass before triggering standby (controlled by Reg0x65[15]). When coming out of standby mode, the normal PLL power-up sequence must be followed as specified in "PLL Power-up" on page 36. Floating Inputs Many MT9D011 signals use bi-directional pins (shown in Table 4 on page 12) for the following three reasons: * The signal associated with the pin is bi-directional in normal use (the only signal in this category is SDATA). * The pin is normally used as an output, but is used as an input during manufacturing test modes (e.g., DOUT[9:0]). * Standard design practice dictates that signal inputs should not be allowed to float for long periods of time. This leads to two areas where the design application should be reviewed: * When using the output-enable control. All MT9D011 bi-directional pins that enter a highimpedance state must be driven to a valid logic level. ( "Output Enable Control" on page 51.) * When input pins are allowed to float. The MT9D011 does not include on-chip pull-down resistors, therefore, no input pins should be allowed to float. Table 15: Signal State During Standby SIGNAL LINE_VALID FRAME_VALID LINE_VALID PIXCLK FLASH DOUT9-DOUT0 STATE 0 0 0 0 0 0 Output-enable control can be used to place the pin interface in a high-impedance state (see "Output Enable Control" on page 51). While in standby, the state of the internal registers is maintained and the sensor continues responding to accesses through its serial register interface. An even lower power standby state can be achieved by stopping the input clock (CLKIN) while in standby. If the input clock is stopped, the sensor does not respond to accesses through its serial register interface. Exit from standby must be through the same mechanism as entry to standby. When the standby source is negated, this sequence occurs: 1. The internal clocks are restarted. 2. The analog circuitry is restored to its normal operating state. 3. The timing and control circuitry performs a restart equivalent to writing Reg0x0D[1] = 1. After this sequence is complete, normal operation resumes. If the input clock is stopped during standby, it must be restarted before leaving standby. Dark Row/Column Display Optically black rows 7 through 0 are used to provide data for black level calibration and are not normally visible in the displayed image. Setting Reg0x22[7] = 1 makes these rows visible in the displayed image. This is achieved by asserting FRAME_VALID earlier than normal, and keeping it asserted longer, so that the following rows are displayed: * The optically black rows at the start of the pixel array (controlled by Reg0x22[2:0]). * Two rows before the visible rows. * The visible rows (controlled by Reg0x01, Reg0x03 and Reg0x20). 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR The result of setting Reg0x22[7] = 1 is a larger image (more rows) than is programmed by Reg0x03. Optically black columns 23 through 0 are used to provide data for row-wise noise cancellations, and are not normally visible in the displayed image. Two methods for making them visible in the displayed image are: * Set Reg0x22[8] = 0 (to disable readout of the dark columns); set Reg0x30[10] = 0 (to disable row-wise correction); then adjust Reg0x02. * Set Reg0x22[9] = 1. When Reg0x22[9] = 1, LINE_VALID is asserted 22 pixel clocks earlier than normal. Data from columns 21 through 2 (20 columns) is followed by two pixel clocks of undefined data, then by data from the visible columns (controlled by Reg0x02, Reg0x04, and Reg0x20). imately 10 flip-flops) is clocked so that access to the two-wire serial interface continues to function correctly. "Power-Saving Modes" on page 53 for more information. Analog Inputs AIN1-AIN3 MT9D011 can share its on-chip ADC resources, such as for use in auto focus applications. If Reg0xE3[15] is set, the chip samples AIN1-AIN3 once per row (after reading out the data from the row). The digital data from this sampling is available to the user in two ways: * Data can be read in registers Reg0xE0 to Reg0xE2 * Data is present in the data stream after LINE_VALID goes low if Reg0xE3[14] is set The nominal range of the AIN pins are 0V + VOFFSET to VREFD + VOFFSET. VREFD is the ADC reference voltage (nominally 1V), but can be programmed. ( "Analog Signal Path" on page 50.) VOFFSET is the offset in the ADC and is typically 10mV to 20mV. If required, the offset can be measured by converting a calibrated reference voltage, which can be used to compensate at the input. The ADC is designed to operate with differential inputs. Since AIN1-AIN3 are used as single-ended inputs to the ADC, it is recommended to average values from several samples (if possible, a whole frame) to cancel out noise. Clock Control The MT9D011 uses an aggressive clock-gating methodology to reduce power consumption: the clocked logic is divided into a number of separate domains, each of which is only clocked as required. Reg0x65 can be used to bypass the clock gating, so that clocks to individual domains run continuously. When the MT9D011 enters a low power state, almost all of the internal clocks are "gated off." The only exception is that a small amount of logic (approx- Figure 32: Timing Diagram AIN1-AIN3 Sample LINE_VALID (1 ADC mode) PIXCLK (1 ADC mode) DATA_OUT (1 ADC mode) PIX PIX X AIN3 X AIN2 X AIN1 LINE_VALID (2 ADC mode) PIXCLK (2 ADC mode) DATA_OUT (2 ADC mode) PIX PIX X AIN3 X AIN2 X AIN1 Power-up Sequence There are no specific requirements to the order in which different supplies are turned on. The reset 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN sequence cannot start before the last supply is stable within the valid ranges as defined in Table 16: DC Electrical Characteristics on page 56. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 54 PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Hard Reset Sequence After power-up, a hard reset is required. Assuming all supplies are stable, the assertion of the RESET# pin to logic "0" will set device in reset mode ~30ns after assertion. The input clock does not have to run while RESET# is active. Release of RESET# will require that the clock is running and after 3 clock cycles (CLKIN), the serial interface is ready to accept commands on the two-wire serial interface. Soft Reset Sequence At any time during normal operation or standby, the user can do a soft reset by writing a logic "1" to Reg0x0D[0] using the two-wire serial interface. This will also put the device in reset mode and all registers (including PLL state and settings) will get their default values. Writing a logic "0" to the same register will release the soft reset, and normal operation can be resumed once the write operation on the serial interface is completed. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Electrical Specifications Table 16: DC Electrical Characteristics (VDD = 1.8V 0.1V; VAA = VAAPIX = VAAPLL = VDDQ = 2.8V 0.3V; TA = Ambient = 25C) SYMBOL VIH VIL IIN VOH VOL IOZ IPWR IPWR Standby NOTE: DEFINITION CONDITION MIN TBD TBD -15 TBD TBD TBD TBD TYP TBD TBD TBD TBD TBD TBD MAX TBD TBD 15 TBD 15 TBD 10 UNITS V V A V V A mA A Input High Voltage Input Low Voltage Input Leakage Current No Pull-up Resistor; VIN = VDD or DGND Output High Voltage Output Low Voltage Tri-state Output Leakage Current Total Quiescent Supply Current2 CLKIN = 36 MHz; default settings Total Standby Supply Current1 STANDBY = VDDQ, CLKIN = 0 MHz 1. To place the chip in standby mode, first raise STANDBY to VDDQ, wait until FRAME_VALID and LINE_VALID are de-asserted, then wait two master clock cycles before turning off the master clock. 2. Summation of currents for all power supplies. Typical operating power does not include the I/O power or the PLL. VAAPLL off, conditions are dark. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Table 17: AC Electrical Characteristics (VDD = 1.8V 0.1V; VDDQ = VAA = VAAPIX = VAAPLL = 2.8V 0.3V; TA = Ambient = 25C; Load Capacitance = TBD) SYMBOL CLKIN t DEFINITION Input Clock Frequency Duty Cycle Input Clock Rise Time Input Clock Fall Time CLKIN to PIXCLK propagation delay, low-to-high CLKIN to PIXCLK propagation delay, high-to-low CLKIN to DOUT[9:0]propagation delay, low-to-high CLKIN to DOUT[9:0] propagation delay, high-to-low Data Hold Time from CLKIN CLKIN to FRAME_VALID and LINE_VALID propagation, low-to-high CLKIN to FRAME_VALID and LINE_VALID propagation, high-to-low CLKIN to FLASH propagation delay, low-to-high CLKIN to FLASH propagation delay, high-to-low CONDITION MIN 4 TYP MAX 40 UNITS MHz % ns ns ns ns ns ns ns R TBD TBD TBD TBD TBD TBD tF t t t PLHP PHLP PLHD tPHLD tOH tPLHF,L tPHLF,L tPHLF tPHLF TBD TBD TBD TBD TBD ns ns ns ns 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Propagation Delay for FRAME_VALID and LINE_VALID The LINE_VALID and FRAME_VALID signals change on the rising edge of the master input clock, as shown in Figure 33. Figure 33: Propagation Delay for FRAME_VALID and LINE_VALID tPLHF,L CLKIN CLKIN tPHLF,L FRAME_VALID LINE_VALID FRAME_VALID LINE_VALID Propagation Delay for PIXCLK and DOUT The DOUT signals change on the rising edge of the master input clock, as shown in Figure 34. LINE_VALID asserts at the same time as the first valid pixel data, at the start of a line, and remains asserted until the end of the final valid pixel data for the line. The timing and behavior of PIXCLK depends on the Reg0x0A settings Figure 34: Propagation Delays for PIXCLK and DOUT Signals tR tF CLKIN tPLHP tPHLP PIXCLK tPLHD, tPHLD tOH DOUT (9:0) DOUT (9:0) DOUT (9:0) DOUT (9:0) DOUT (9:0) 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Two-Wire Serial Bus Timing The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles. Figure 37: Serial Host Interface Write Data Timing 4 SCLK 4 Figure 35: Serial Host Interface Start Condition Timing 5 SCLK 4 SDATA NOTE: SDATA is driven by an off-chip transmitter. SDATA Figure 38: Serial Host Interface Read Data Timing 5 Figure 36: Serial Host Interface Stop Condition Timing 5 SCLK 4 SCLK SDATA NOTE: SDATA SDATA is pulled low by the sensor, or allowed to be pulled high by an off-chip pull-up resistor. NOTE: All timing in master clock cycle units. Figure 39: Acknowledge Signal Timing Following 8-Bit Write to Sensor 6 SCLK Sensor pulls down SDATA pin 3 SDATA Figure 40: Acknowledge Signal Timing Following 8-Bit Read from Sensor 7 SCLK Sensor tri-states SDATA pin (turns off pull down) 6 SDATA NOTE: After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no-acknowledge by leaving SDATA to float high. On the following cycle, a start or stop bit can be used. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. MICRON CONFIDENTIAL AND PROPRIETARY PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Figure 41: Spectral Response (TBD) Data Sheet Designation Preliminary: This data sheet contains initial characterization limits that are subject to change on full characterzation of production devices. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 60 MICRON CONFIDENTIAL AND PROPRIETARY PRELIMINARY MT9D011 2-MEGAPIXEL DIGITAL IMAGE SENSOR Revision History Rev A, Preliminary .........................................................................................................................................................11/04 * Initial Release of document (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef81516da4 MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 61 |
Price & Availability of MT9D011
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |